IBM has demonstrated the world’s first sub-1 nanometer chip technology with a 0.7 nm, or 7 angstrom, transistor architecture and nearly double the transistors of the 2 nm chip the company unveiled in 2021.
For the purpose of clarity, the 0.7 nm reference is a label for this generation of chip-making rather than the actual width of anything as modern transistors aren’t really that size. But it signals that IBM has pushed past the 1 nm mark for the first time.
With this new architecture IBM was able to pack nearly 100 billion transistors onto a chip the size of a fingernail. The chip is projected to deliver up to 50 percent more performance, or 70 percent better energy efficiency, than IBM’s 2 nm chips allowing designers to choose where to spend the improvement. This solution is said to vastly improve the compute power required for generative AI, cloud infrastructure, and electronic devices.
“IBM’s latest chip breakthrough marks a landmark moment in computing, pushing technology beyond the nanometer era to the scale of atoms. With our new nanostack architecture, we’re not just making smaller transistors, we’re reinventing how chips are built to deliver dramatically more power and energy efficiency,” Jay Gambetta, Director of IBM Research and IBM Fellow, said in a press release. “This industry-first innovation continues IBM’s legacy of leading in next-generation technologies and sets the foundation for the next era of computing.”
To create this chip, IBM developed nanostack, a new three-dimensional nanosheet-based design. This design sees transistors stacked and staggered vertically in order to pack more transistors onto the chip.
The chip has been experimentally validated through ultra-thin dielectric bonding in CMOS integration, demonstration of dual-channel engineering capability, and functional CMOS inverter operation. In this testing, IBM confirmed the design can actually be built and can run real computing tasks, not just exist on paper.
Furthermore, IBM researchers demonstrated at VLSI 2026 that nanostack architecture provides 40 percent scaling in static memory, allowing designers to create efficient chips that support the high-bandwidth demands of AI workloads.
The firm notes that this development demonstrates that continued angstrom-level scaling is possible and dimensions may soon approach the size of individual atoms.
IBM says the technology could reach production in as little as five years, with its roadmap projecting at least a decade of scaling still to come. This is a landmark development for the chip industry that has had to contend with the physical limitations of traditional scaling.