AI data centre development is entering a more complex and capital-intensive phase, according to Taiwan-based analysts TrendForce who have laid out what they think the key trends will be in 2026. This new phase is due to growth in AI workloads beginning to expose structural constraints across compute, cooling, memory, power delivery and energy storage.
What had previously been incremental upgrades across these domains is now becoming a coordinated redesign of AI infrastructure, driven by escalating chip power densities, bandwidth bottlenecks, and the operational realities of large-scale AI clusters.
TrendForce forecasts that AI server shipments will grow by more than 20 percent year-on-year in 2026, supported by sustained capex from major North American cloud service providers and the rapid emergence of sovereign cloud initiatives across multiple regions. While the pace of AI deployment remains strong, the nature of that deployment is changing. Infrastructure decisions are increasingly dictated by physical limits – thermal, electrical, and architectural – rather than purely by software ambition or model size.
This shift is most visible in the intensifying competition within the AI chip market, where rising performance requirements are driving both higher power consumption and deeper vertical integration across the supply chain.
AI chip competition expands
Nvidia remains the dominant supplier of AI accelerators, but TrendForce expects competitive pressure to increase significantly over the next two years. AMD is preparing to challenge Nvidia more directly with its MI400 full-rack solution, which mirrors Nvidia’s GB200 and forthcoming GB300 system-level architectures and is explicitly targeted at hyperscale CSP deployments rather than standalone accelerator cards.
At the same time, major US hyperscalers are accelerating their in-house ASIC development strategies. These efforts are not positioned as full replacements for Nvidia GPUs in the short term, but rather as workload-specific accelerators designed to reduce cost, improve power efficiency, and lessen dependence on third-party roadmaps.
In China, geopolitical constraints and export controls are accelerating a parallel push towards domestic AI chip ecosystems. Companies including ByteDance, Baidu, Alibaba, Tencent, Huawei, and Cambricon are all increasing investment in proprietary AI silicon. TrendForce notes that this drive for technological self-sufficiency is reshaping global competition, with Chinese vendors prioritising architectural independence and supply chain resilience alongside raw performance.
Across all regions, however, one unifying trend is the rapid escalation of chip-level thermal design power. Nvidia’s H100 and H200 GPUs, rated at around 700W, are already stretching conventional air-cooling limits. The upcoming B200 and B300 platforms are expected to exceed 1,000W per chip, fundamentally altering server and rack-level thermal design assumptions.
Liquid cooling moves to default
In 2026, as chip power densities rise, liquid cooling is shifting from a specialised solution to a mainstream requirement within AI data centres. TrendForce estimates that liquid-cooled server racks will account for approximately 47 percent of deployments by 2026, reflecting the inability of traditional air cooling to manage sustained high-density AI workloads efficiently.
In the near to mid-term, cold-plate liquid cooling is expected to remain the dominant approach. This method provides a balance between thermal performance, operational familiarity, and integration cost, particularly for data centre operators retrofitting existing facilities. Coolant distribution units are also evolving, with liquid-to-liquid CDUs gradually replacing liquid-to-air designs as facilities seek higher efficiency and tighter thermal control.
Microsoft’s introduction of chip-level microfluidic cooling illustrates the direction of travel for longer-term thermal management. By integrating cooling channels directly into chip packages, microfluidic approaches promise further gains in heat removal efficiency while reducing thermal gradients across increasingly complex multi-die packages. TrendForce does not expect these techniques to see widespread adoption in the immediate term, but views them as a critical pathway as chip TDP continues to rise.
The expansion of liquid cooling has broader implications beyond mechanical systems. It influences rack layouts, floor loading, maintenance practices, and energy efficiency metrics, reinforcing the idea that AI data centre design is becoming an exercise in system-level optimisation rather than component substitution.
Bandwidth becomes the next bottleneck
While thermal constraints are driving visible changes in facility design, TrendForce argues that bandwidth limitations, both within and between chips, are emerging as the next major performance bottleneck for AI systems in 2026.
AI workloads are no longer dominated solely by training. Inference at scale, particularly for large language models and multimodal systems, is placing sustained pressure on memory bandwidth and interconnect efficiency. Current generations of high-bandwidth memory, built on 3D stacking and through-silicon via technologies, have significantly reduced the physical distance between processors and memory, delivering major gains in throughput and energy efficiency.
The forthcoming HBM4 generation will extend these gains by increasing channel density and widening I/O bandwidth, enabling closer alignment with the growing computational capabilities of AI GPUs and accelerators. However, TrendForce cautions that as model parameters move beyond the trillion-scale and GPU clusters continue to expand, memory bandwidth once again becomes a limiting factor.
Memory suppliers are responding through a combination of architectural optimisation, packaging innovation, and co-design with logic chips. These efforts aim to maximise on-chip bandwidth and reduce latency, but they do not fully address the challenges of data movement across chips, modules, and racks.
Optical interconnects reshape AI clusters
As electrical interfaces struggle to scale efficiently over longer distances and higher data rates, optical technologies are now at the forefront of AI system design. TrendForce highlights co-packaged optics and silicon photonics as strategic priorities for both GPU vendors and cloud service providers.
Pluggable optical transceivers operating at 800G and 1.6T have already entered mass production, supporting current-generation AI clusters. From 2026 onwards, higher-bandwidth silicon photonics and CPO platforms are expected to be deployed within AI switches, enabling denser, lower-power interconnects between compute nodes.
These optical advances are not merely incremental upgrades. They represent a shift in how AI clusters are architected, reducing reliance on traditional electrical signalling and enabling larger, more tightly coupled systems without proportional increases in power consumption. TrendForce views high-speed optical transmission as a foundational pillar of next-generation AI infrastructure, alongside advances in compute and memory.
Storage adapts to AI inference realities
AI workloads are also reshaping enterprise storage strategies. Training and inference both require rapid access to large datasets, often with unpredictable I/O patterns that expose limitations in conventional storage architectures.
NAND Flash suppliers are addressing this gap through two distinct product categories. The first focuses on ultra-low-latency solutions positioned between DRAM and traditional NAND, including storage-class memory SSDs, KV cache SSDs, and HBF. These technologies are designed to accelerate real-time inference by reducing latency and improving bandwidth consistency.
The second category targets capacity-driven storage needs through nearline QLC SSDs. These drives are increasingly used for warm and cold data tiers, such as model checkpoints and dataset archives. QLC technology offers approximately 33 percent higher per-die storage density than TLC, significantly reducing cost per bit for large-scale AI data retention.
TrendForce forecasts that QLC SSDs will account for around 30 percent of the enterprise SSD market by 2026, reflecting their growing role in balancing performance and cost within AI storage stacks.
Energy storage becomes core infrastructure
Power stability is emerging as a defining challenge for AI data centres in 2026, particularly as clustered architectures introduce highly variable and spiky load profiles. TrendForce argues that energy storage systems are evolving from supplementary backup solutions into core infrastructure components.
Over the next five years, medium- to long-duration energy storage, typically in the two- to four-hour range, is expected to grow rapidly. These systems will support not only backup power and power quality management, but also energy arbitrage and grid services.
Deployment models are also shifting. Centralised, facility-level battery systems are giving way to more distributed architectures, with rack- or cluster-level modular battery units capable of near-instantaneous response. This approach improves resilience while aligning more closely with the decentralised nature of AI compute clusters.
Globally, TrendForce projects installed AI data centre energy storage capacity to grow from 15.7 GWh in 2024 to 216.8 GWh by 2030, representing a compound annual growth rate of 46.1 percent. North America is expected to lead this expansion, driven by hyperscale providers, while China’s “Eastern Data, Western Computing” initiative is accelerating deployment of AI campuses paired with large-scale energy storage in renewable-rich regions.
800V HVDC and the rise of wide-bandgap chips
As racks move from kilowatt to megawatt-scale designs, TrendForce observes rapid adoption of 800V high-voltage DC systems, which offer improved efficiency, reduced copper usage, and more compact power delivery.
Third-generation semiconductors, particularly silicon carbide and gallium nitride, are central to this transition. SiC devices are increasingly used in front-end and mid-stage power conversion, where they handle high voltages and loads while offering superior thermal and switching performance. Although current SiC devices have lower maximum voltage ratings than traditional silicon, their efficiency advantages make them critical to the development of solid-state transformers.
GaN, meanwhile, is gaining traction in mid- and end-stage conversion, where its high-frequency characteristics support ultra-high power density and fast dynamic response. TrendForce expects SiC and GaN adoption in data centre power systems to reach 17 percent by 2026 and exceed 30 percent by 2030.
Semiconductor integration underpins the next cycle
Underlying all of these trends is a broader transformation in semiconductor manufacturing. The industry is simultaneously pushing towards 2nm process nodes using GAAFET architectures, while expanding into larger, more complex packages through 2.5D and 3D heterogeneous integration, according to TrendForce.
Foundries including TSMC, Intel, and Samsung are pursuing distinct packaging strategies – CoWoS and SoIC, EMIB and Foveros, and I-Cube and X-Cube respectively – as they ramp 2nm production. These approaches are designed to integrate multiple dies with different functions and process nodes into single packages optimised for AI and HPC workloads.
Rather than a simple race towards ever-smaller process nodes, the next phase of semiconductor development is shaping up as a test of industrial execution. As chipmakers push simultaneously into 2nm production and increasingly complex 2.5D and 3D packages, questions of capacity planning, yield, cost control, and long-term reliability become as strategically important as transistor density itself.
In this environment, TrendForce reckons competitive advantage is likely to favour those able to deliver scalable, manufacturable platforms that map cleanly onto the emerging realities of AI data centre design, as opposed to firms pursuing process leadership in isolation.